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Important Dates for Volume & Issue     Paper Submission : 31-07-2017   Frequency : 12 Issues per Year

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Sr No.

Title of Paper

I. LOW-POWER PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES USING VERILOG HDL

Authors: Konki Puram Laxman Sai Supra Sidhu, Dr. Shaik Meeravali   

Page No.: 1 - 9  

II. ALGORITHM-BASED FAULT CORRECTION USING BLOOM FILTERS FOR COMMUNICATION APPLICATIONS

Authors: Vempati Rohith Mohan, Saggurti Nageswar Rao, Madhala Swathi, Gandhi. B   

Page No.: 10 - 16  

III. VLSI IMPLEMENTATION OF ALU DESIGN USING QSD IN FPGA TECHNOLOGY

Authors: P. Shailaja, S. Shankaran, Dr. D. Nageshwarrao   

Page No.: 17 - 24  

VI. WIND ENERGY CONVERSION SYSTEMS BY DOUBLY FED INDUCTION GENERATOR WITH INTEGRATED ACTIVE FILTER CAPABILITIES  AND CONTROL BY USING FUZZY

Authors: Pusa Srikanth, G. Upendra Rao   

Page No.: 25 - 33  

V. A FUZZY LOGIC BASED WIND ENERGY CONVERSION SYSTEM USING DOUBLY FED INDUCTION GENERATOR WITH ACTIVE FILTER

Authors: M. Goutham Kumar, K. Chandra Shekar, T. Kranthi Kumar, M. Satish Kumar   

Page No.: 34 - 42  

VI. ATTRIBUTE-BASED ENCRYPTION TECHNIQUE FOR CLOUD COMPUTING

Authors: Hafsa Mohammadi, Mr. Mohd Anwar Ali, S. Md Ismail   

Page No.: 43 - 46  

VII. A SMOOTH STARTER FOR A DC MOTOR BASED ON FUZZY LOGIC CONTROL BY USING BUCK POWER CONVERTER

Authors: Byri Swamy, A. Gopala Krushna   

Page No.: 47 - 58  

VIII. VERILOG HDL IMPLEMENTATION OF ARITHMETIC COSINE TRANSFORM IN FPGA TECHNOLOGY

Authors: B. Mounika Reddy, Dr. D. Nageshwarrao   

Page No.: 59 - 70  

IX. VLSI DESIGN OF A HIGH SPEED NOVEL ARCHITECTURE OF BLOOM FILTERS

Authors: Kammari Swetha, G. Deepika   

Page No.: 71 - 76  

X. A STUDY ON STRENGTH PROPERTIES OF GLASS POWDER CONCRETE

Authors: Uppunuthula Poornamachary, Syed Moizuddin   

Page No.: 77 - 81  

XI. AREA DELAY EFFICIENT FM0/MANCHESTER ENCODING USING SOLS TECHNIQUE FOR COMMUNICATION APPLICATIONS

Authors: Rayabharapu Mounika, A. Akhila, B. Nihar   

Page No.: 82 - 89  

XII. A HIGH-PERFORMANCE MULTICELL TOPOLOGY BASED ON SINGLE-PHASE POWER CELLS FOR POWER QUALITY IMPROVEMENT

Authors: Y. Sireesha, Jawabu Naveez Bhanutej   

Page No.: 90 - 101  

XIII. DESIGN AND COMPARISON OF REED SOLOMON DECODER ON TWO DIFFERENT FPGA USING VERILOG HDL

Authors: Jayaram Manasa, G. Venkata Subba Rao, Dr. D.Nageshwar Rao   

Page No.: 102 - 107  

XIV. A FUZZY BASED POWER OSCILLATION DAMPING CONTROLLER USING STATCOM WITH ENERGY STORAGE

Authors: K. Rajashekar, E. Prasanna, T. Kranthi Kumar   

Page No.: 108 - 116  

XV. NEW VLSI ARCHITECTURE FOR EXPLOITING CARRY-SAVE ARITHMETIC USING VERILOG HDL

Authors: B. Anusha, Ch. Ramesh   

Page No.: 117 - 121  

XVI. ERROR DETECTING AND CORRECTING CODE USING ORTHOGONAL LATIN SQUARE CODES IN FPGA TECHNOLOGY

Authors: R. Bhavani, P. V. Varaprasad Rao   

Page No.: 122 - 126  

XVII. A CONTROL STRATEGY OF FUZZY BASED THREE-PHASE INVERTER IN DISTRIBUTED GENERATION

Authors: Beeravoluchandana, Mr. M. Santhosh   

Page No.: 127 - 137  

XVIII. IMPLEMENTATION OF 19-LEVEL CASCADING FLYING CAPACITOR AND FLOATING CAPACITOR H-BRIDGES INVERTER USING FUZZY  LOGIC

Authors: Ruquia Quraishi, B. Durga Naik   

Page No.: 138 - 146  

XIX. AREA DELAY EFFICIENT FM0/MANCHESTER ENCODING USING SOLS TECHNIQUE FOR COMMUNICATION APPLICATION

Authors: A.Vaani, D. Rupa kumar, K Srinivasa Reddy   

Page No.: 147 - 155  

XX. MODULAR MULTILEVEL CONVERTER FOR VARIABLE SPEED DRIVES WITH FUZZY LOGIC CONTROL

Authors: Suklaja Donuru, Mr. M. Sai Prasad Reddy   

Page No.: 156 - 164  

XXI. SIMULATION OF FUZZY BASED MODULAR MULTILEVEL DC/DC CONVERTER WITH FAULT BLOCKING CAPABILITY FOR HVDC  INTERCONNECTS

Authors: B. Karnakar, E. Prasanna, T. Kranthi Kumar   

Page No.: 165 - 176  

XXII. RATE AND POWER CONTROL BASED ENERGY SAVING TRANSMISSIONS IN OFDMA BASED MULTICARRIER BASE STATIONS

Authors: K. Sampath Kumar, K Praveen, R. Ramesh Babu   

Page No.: 177 - 185  

XXIII. DESIGN AND IMPLEMENTATION OF ERROR DETECTING AND CORRECTING CODE USING REED SOLOMON CODES

Authors: Nousheen Begum, B. Praveen Kumar, K. Hymavathi   

Page No.: 186 - 191  

XXIV. FUZZY BASED COMPARISON OF ELECTRICSPRINGS WITH STATCOM FOR DISTRIBUTED VOLTAGE CONTROL

Authors: B. Krishna Kanth, E. Prasanna, T. Kranthi Kumar   

Page No.: 192 - 203  

XXV. DESIGN AND IMPLEMENTATION OF AREA EFFICIENT FM0/MANCHESTER ENCODING SCHEME

Authors: N. C. Prem Kumar, G. Deepika   

Page No.: 204 - 211  

XXVI. A FUZZY BASED BIDIRECTIONAL AC/DC OR DC/AC CONVERTER FOR ELECTRICAL VEHICLE AND DC OR AC GRID

Authors: K. Sushma, M. Satish Kumar, T. Kranthi Kumar   

Page No.: 212 - 221  

XXVII. DESIGNING OF MULTI STAR EDIFICE USING POST-TENSIONED SLABS

Authors: Adimulam Srinath, K. Rakesh Reddy, B. Srinath   

Page No.: 222 - 227  

XXVIII. LOW POWER DESIGN OF A RAM USING PULSED LATCHES BASED SHIFT REGISTER

Authors: M. Harinayak, Nilofer Lalani, G. Deepika   

Page No.: 228 - 233  

XXIX. PROTECTING DSP CIRCUITS THROUGH OBFUSCATION VIA HIGH-LEVEL TRANSFORMATIONS IN FPGA TECHNOLOGY

Authors: Nampelli Suresh, B. Vasu Naik   

Page No.: 234 - 241  

XXX. IMPLEMENTATION OF PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES USING VERILOG HDL

Authors: Eerati Anitha, M. Nagaraju, K. Hymavathi   

Page No.: 242 - 250  

XXXI. DESIGN AND IMPLEMENTATION OF ARITHMETIC COSINE TRANSFORM IN FPGA TECHNOLOGY

Authors: Bashamoni Jyothsna, M. Harinath Reddy, S. Venumadhav   

Page No.: 251 - 262  

XXXII. FUZZY LOGIC CONTROLLER BASED RESONANCE PROPAGATION AND MITIGATION IN GRID-CONNECTED AND ISLANDING  MICROGRIDS

Authors: L. Dinesh Babu, V. Satyavardhan Rao , T. Kranthi Kumar   

Page No.: 263 - 273  

XXXIII. SIMULATION OF FUZZY PV-ACTIVE POWER FILTER COMBINATION SUPPLIES POWER TO NONLINEAR LOAD AND CONTROL UTILITY  CURRENT

Authors: P. Yamini, T. Kranthi Kumar   

Page No.: 274 - 282  

XXXIV. SECURED MICROCONTROLLER BASED BIO-METRIC AUTHENTICATED ELECTRONIC VOTING MACHINE USING GSM TECHNOLOGY

Authors: P. Rajitha, K. Prashanth   

Page No.: 283 - 289  

XXXV. IMPLEMENTATION OF PRE-ENCODED MULTIPLIERS BASED ON NR4SD ENCODING TECHNIQUE FOR DSP/MULTIMEDIA APPLICATIONS

Authors: B. Sunny Manohar, M. Chandra Shekar, B. Ramu   

Page No.: 290 - 300  

XXXVI. REPLACEMENT OF COARSE AGGREGATES WITH COCONUT SHELL AND COIR IN CONCRETE

Authors: Polleboina Vani, P. Ramakrishna, K. Anand Reddy   

Page No.: 301 - 306  

XXXVII. IMPLEMENTATION ENHANCED MAJORITY LOGIC DECODING OF LOW DENSITY PARITY CHECK CODES FOR ERROR DETECTION

Authors: Nandi Manjula, K. Anil Kumar   

Page No.: 307 - 313  

XXXVIII. IMPLEMENTATION OF PARALLEL FILTER USING ERROR CORRECTION CODES IN DIGITAL SIGNAL PROCESSING CIRCUITS

Authors: Safeeya Sulthana, B. Ramu   

Page No.: 314 - 319  

XXXIX. DATA DISSEMINATION IN VEHICULAR CLOUD SYSTEMS USING PRE FETCHING

Authors: Gundalavijayendar, D. Rupakumar, Dr. K. Srinivas Reddy   

Page No.: 320 - 325  

XXXX. PRIVACY POLICY INFERENCE OF USER-UPLOADED IMAGES OR TEXT ON CONTENT SHARING AND RETRIEVING DATA ON WEB  SERVICES

Authors: Padam Srilatha, Mrs. P. Aswani   

Page No.: 326 - 329  

XXXXI. NEW ARCHITECTURE FOR PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES USING VERILOG HDL

Authors: B. Anusha, T. Swetha, B. Ramu   

Page No.: 330 - 339  

XXXXII. MODIFIED BOOTH RECODER FOR EFFICIENT ADD-MULTIPLY OPERATOR

Authors: Mahamud Mahabubkhan, Treasa Jincy Joseph, Stalin   

Page No.: 340 - 349  

XXXXIII. GPRS BASED SAFETY TRANSPORTATION SYSTEM FOR SCHOOL CHILDRENS

Authors: M Premalatha, S. Vijayalaxmi   

Page No.: 350 - 354  

XXXXIV. DESIGN AND ANALYSIS OF HELICAL GEAR

Authors: T. Subba Reddy, Dvsrbm Subhramanyam   

Page No.: 355 - 360  

XXXXV. NEW VLSI ARCHITECTURE FOR EXPLOITING CARRY-SAVE ARITHMETIC USING VERILOG HDL IN FPGA TECHNOLOGY

Authors: P. Bal Kumar Reddy, B. Ramu   

Page No.: 361 - 366  

XXXXVI. DESIGN AND IMPLEMENTATION OF HIGH THROUGHPUT FINITE FIELD MULTIPLIER USING REDUNDANT BASIS TECHNIQUE

Authors: G. Rakesh Reddy, B. Ramu   

Page No.: 367 - 372  

XXXXVII. AN EFFICIENT ADAPTIVE PRIVACY POLICY PREDICTION APPROACH FOR USER UPLOADED IMAGE ON CONTENT SHARING SITES

Authors: Dr K. Jagan Mohan, Jyothi Kondabathula, G. Divya   

Page No.: 373 - 378  

XXXXVIII. VLSI DESIGN OF HIGH SPEED PARTIALLY PARALLEL ENCODER ARCHITECTURE

Authors: Kankanala Satish Kumar, G. Deepika   

Page No.: 379 - 388  

XXXXIX. FUZZY LOGIC CONTROLLER BASED INTELLIGENT ISLANDING AND SEAMLESS RECONNECTION TECHNIQUE FOR MICRO GRID AND  UPQC WITH POWER GRID

Authors: D. Sirisha, M. Ragini, T. Kranthi Kumar   

Page No.: 389 - 397  

XXXXX. MAT LAB AND ANDROID BASED ASSISTIVE SYSTEM FOR OBJECT IDENTIFICATION OF BLIND PERSONS

Authors: Shanku Vinod, P. Praveen Raju   

Page No.: 398 - 404  

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