IMPACT FACTOR : 3.250
Important Dates for Volume & Issue     Paper Submission : 30-11-2017   Frequency : 12 Issues per Year

Current Issues


Sr No.

Title of Paper

I. IMPLEMENTATION OF DATA ENCODING TECHNIQUES FOR REDUCING AREA, POWER CONSUMPTION IN NETWORK-ON-CHIP  USING  FPGA TECHNOLOGY

Authors: T. Vamsidhar, K. Yogithabali   

Page No.: 1 - 8  

II. AN OPTIMIZED IMPLEMENTATION OF HIGH THROUGHPUT AGING-AWARE RELIABLE MULTIPLIER WITH VARIABLE LATENCY

Authors: K. Lakshmi Prasanna, D. Poornachandra Reddy   

Page No.: 9 - 16  

III. A REVOCABLE MULTI-AUTHORITY CP-ABE FRAMEWORK FOR EFFICIENT ATTRIBUTE REVOCATION

Authors: T. Deepthi, G. Lakshmi Kanth   

Page No.: 17 - 22  

IV. DESIGN OF ENCODER & DECODER TO MINIMIZE POWER CONSUMPTION IN NETWORK ON CHIP BASED ON VERILOG

Authors: D. Vimalajyothi, C. Madhavi   

Page No.: 23 - 31  

V. AN ADVANCED CONTROLLER WITH ACTIVE POWER FILTER UNDER RENEWABLE POWER GENERATION SYSTEMS

Authors: Mohd. Mustafa , Dr. V. Balakrishna Reddy, G. Revan Sidda   

Page No.: 32 - 37  

VI. AREA EFFICIENT LOW POWER DOUBLE-TAIL COMPARATOR USING SWITCHING TRANSISTORS

Authors: L . Venkateswarlu, MA .Wajeed, M. Basha   

Page No.: 38 - 45  

VII. DESIGN OF HIGH SPEED MULTIPLER USING MULTI OPERAND ADDER TREES

Authors: Vijayagiri Niveditha,P. Anuradha   

Page No.: 46 - 51  

VIII. A LOW POWER MULTIBAND CLOCK DISTRIBUTATION USING TRUE SINGLE PHASE CLOCK

Authors: Ishrath Begum, K. Rajkumar   

Page No.: 52 - 57  

IX. CLOUD CONSISTENCY AS A SERVICE AUDITING

Authors: T. Aruna, G. Sailaja   

Page No.: 58 - 62  

X. VLSI IMPLEMENTATION OF INTEGER DCT ARCHITECTURES FOR HEVC IN FPGA TECHNOLOGY

Authors: M. Devendra, P. Giribabu   

Page No.: 63 -74  

XI. PAPR REDUCTION USING THE PIECEWISE LINEAR TRANSFORMATION IN THE OFDM WITH LESS COMPANDING DISTORTION

Authors: T. Praveen Kumar, Mr. N. Vasu   

Page No.: 75 -80  

XII. AN EFFCIENT WAY TO DETECT THE DUPLICATE DATA IN CLOUDS BY USING TRE MECHANISAM

Authors: Umakant Dashrath Khapane, N. Sujatha Choudhary   

Page No.: 81 -87  

XIII. AN OPTIMIZED IMPLEMENTATION OF LMS ADAPTIVE FILTER USING PARTIAL PRODUCT GENERATOR WITH LOW ADAPTATION  DELAY  IN FPGA TECHNOLOGY

Authors: G. Vishali, V. Santhosh Kumar, M. Basha   

Page No.: 88 -95  

XIV. DETECTION OF VEHICLE LOCATION AND ITS EMISSIONS USING RFID TECHNOLOGY ON INTERNET OF THINGS

Authors: Kurnuthala Sirisha, K. Niranjan Reddy   

Page No.: 96 -100  

XV. RASP PERTURBATION APPROACH TO HOSTING QUERY SERVICES IN THE CLOUD

Authors: S. Ramasubba Reddy, N. Siddaiah   

Page No.: 101 -107  

XVI. AN AREA DELAY EFFICIENT DESIGN OF FAM USING MODIFIED BOOTH RECODER

Authors: A. Swetha, B. Swapna Rani   

Page No.: 108 -115  

XVII. FUZZY LOGIC CONTROL BASED VOLTAGE STABILITY ANALYSIS OF ELECTRIC RAILWAY SYSTEM USING SFCL

Authors: S. Anuradha, M. Vijaya Kumar   

Page No.: 116 -122  

XVIII. VLSI DESIGN OF LMS ADAPTIVE FIR FILTER FOR HIGH SPEED APPLICATION

Authors: Sarsan Tapasiya Reddy, J. Sunitha Kumari   

Page No.: 123 -130  

XIX SAFE INFORMATION RECOVERY FOR DISTRIBUTED INTERRUPTION-LENIENT MILITARY NETWORKS

Authors: A. M. Nalini, N. Jaya Krishna   

Page No.: 131 -138  

XX EFFICIENT IMPLEMENTATION OF PARALLEL SELF-TIMED ADDER USING FPGA TECHNOLOGY

Authors: Y. Nikhila, D. M. K. Chaitanya   

Page No.: 139 -145  

XXI FUZZY LOGIC CONTROL BASED VOLTAGE STABILITY ANALYSIS OF ELECTRIC RAILWAY SYSTEM USING SFCL

Authors: S. Anuradha, M. Vijaya Kumar   

Page No.: 146 -152  

XXII A GAME THEORY TO LOAD BALANCING STRATEGY OF CLOUD PARTITIONING FOR THE PUBLIC CLOUD

Authors: A. Neelima, G. Lakshmi Kanth   

Page No.: 153 -158  

XXIII EXCITATION SYNCHRONOUS WIND POWER GENERATOR WITH MAXIMUM POWER TRACKING SCHEME

Authors: Divya Tammisetti, Kranti Kiran Tummala   

Page No.: 159 -166  

XXIV THREE EIRQ SCHEMES BASED ON AN ADL TO PROVIDE DIFFERENTIAL QUERY SERVICES

Authors: D. Kartheek, N. Siddaiah   

Page No.: 167 -172  

XXV AN EFFICIENT IMPLEMENTATION OF LMS ADAPTIVE FILTER WITH LOW ADAPTATION DELAY

Authors: Kodimella Mahendar, Ch. Ravi   

Page No.: 173 -178  

XXVI DESIGN AND IMPLEMENTATION OF INTEGER DCT ARCHITECTURES FOR HEVC IN FPGA TECHNOLOGY

Authors: R. Raju, Ch. Ravi   

Page No.: 179 -192  

XXVII DISTRIBUTED, CONCURRENT, AND INDEPENDENT ACCESS TO ENCRYPTED CLOUD DATABASES

Authors: E. D. Pavanakumar, N. Siddaiah   

Page No.: 193 -198  

XXVIII HIGHLY SCALABLE TWO-PHASE TDS APPROACH TO ELIMINATE SCALABILITY PROBLEM OF LARGE-SCALE DATA ANONYMIZATION

Authors: C. S. M Jaswanth, N. Siddaiah   

Page No.: 199 -203  

XXIX PERSONALIZED QUERY BASED SEARCH TECHNIQUES BASED ON CONTENT AND LOCATION CONCEPT

Authors: B. Santhosh Kumar, N. Jayakrishna   

Page No.: 204 -209  

XXX A NEW VLSI ARCHITECTURE FOR MULTIPLICATION USING RADIX-10 MODIFIED BOOTH ENCODING TECHNIQUE

Authors: Akshata Koppa, Manjula. S   

Page No.: 210 -221  

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